Optical interconnect networks

ABSTRACT

An optical interconnect network has four stages (S 4  to S 7 ) each formed from two-dimensional perfect shuffle interconnect stage (6) and a two-dimensional array of processing modules (8) each of which has a two-dimensional array of inputs and outputs. The use of two-dimensional modules provides an increase in optical channels which can be processed compared to the equivalent one-dimensional modules. The modules can perform switching functions.

Many one dimensional (linear) networks have been proposed for a varietyof purposes which have a number of parallel channels which are processedby several distinct stages in a pipelined manner. Each stage can besplit into two parts: an interconnect stage where the lines are permutedfollowed by a layer of two-input two-output processing modules whichoperates on adjacent pairs of data channels.

Recently, efficient optical computers have been proposed which arenetworks where the interconnect part is performed using optics and themodule part in some other medium, for example a chip of lithium niobatedirectional couplers (P. Granestrand et al, "Strictly non-blocking 8×8integrated optical switch matrix" Electron. Lett. 22 No. 15 (1986)) oran optoelectronic integrated circuit (J. E. Midwinter, "Novel approachto optically activated wideband switching matrices" IEEE Proc. J 134 261(1987)). Such machines have the physical layout described above. The useof optics for the interconnect stage has the advantages of highbandwidth, zero time skew and low crosstalk which give the wholeprocessor a high throughout of parallel data. The variousinterconnection patterns which the networks employ can be generatedusing bulk or holographic optical components. Such an arrangement doesnot, however, take full advantage of the parallelism possible withoptical systems.

Shing-Hong Lin et al in an article entitled "2-D Optical MultistageInterconnection Networks", SPIE Vol 752 Digital Optical Computing (1987)pp 209-216, describe the use of 2-D networks employing 2-D perfectshuffles interconnects and 2-D four-input, four output processingmodules. Lin et al give no indication of the control structure necessaryto achieve any particular network interconnection but rather point outthat full, 24 cross-bar switches can in principle achieve a desiredconfiguration.

It is an object of the present invention to provide an opticalinterconnect network having less structural complexity than such known2-D networks. Accordingly an optical interconnect network comprises atleast one stage which has an optical interconnect stage connecting atwo-dimensional array of interconnect input ports to a two-dimensionalarray of interconnect output ports and an array of optical processingmodules each having a two-dimensional array of module input ports,optically coupled to a respective interconnect output port, and a twodimensional array of module output ports characterised in that eachmodule is functionally identical to a first and a second pair oftwo-input, two-output processing sub-modules in which each input of eachof the second pair of processing sub-modules is connected to an outputof a respective distinct one of the first pair of processingsub-modules.

The two dimensional network can be assembled using optics, with similarperformance as before. There is a limit to the number of channels whichcan be accommodated which is proportional to either the maximum width ofhe module element or to the distance across which the optics can imagefaithfully. If this limit is N channels in the case of a one dimensionalnetwork then it becomes N² for a two dimensional one. A furtheradvantage of a network according to the present invention is that anetwork of a given size can be built much more compactly in a twodimensional form.

Because the present invention requires only a sufficient number ofprocessing elements as are necessary to carry out the same processing asthe four sub-modules, the structural complexity is reduced from thatrequired to provide a full 4×4 processing yet, as will be shown later,it can be functionally identical to a concatenation of the processingmodules of a one dimensional network and have the same controlstructure.

The present invention therefore allows the use of one dimensionalnetwork control structure with two-dimensional optical networks.

An embodiment of the present invention will now be described, by way ofexample only, with reference to the accompanying drawings, of which:

FIG. 1 is a schematic generalised diagram of prior art one-dimensionalnetworks;

FIGS. 2a and 2b are schematic diagrams of an exchange and by-pass moduleused in an interconnection network as shown in FIG. 1;

FIG. 3 is a schematic generalised diagram of an two dimensionalinterconnect network according to the present invention;

FIG. 4 is a schematic diagram of an exemplary one-dimensional networkwhich can be configured as a two-dimensional network according to thepresent invention;

FIG. 5 is a schematic diagram of one of the modules of the FIG. 3embodiment of the present invention when reproducing the functionalityof the network of FIG. 4;

FIG. 6 is a schematic diagram to show the functional equivalence of atwo dimensional processing module of the present invention to four onedimensional sub-modules; and

FIG. 7 is a schematic diagram illustrating the condition for whichstages of a one-dimensional network can be concatenated to form atwo-dimensional network according to the present invention.

Referring to FIG. 1 is a generalised one-dimensional, prior artinterconnect network comprises three stages S₁ -S₃ each having aone-dimensional interconnect stage 2 and a layer of two-input,two-output processing modules 4. The interconnections at each stage canbe different as can the functions performed by the modules.

Networks which fall into the general description above can be made to domany parallel processing tasks. The most common function is to have anumber of data streams at the input, and to have the output be the samedata lines in a different order, the order to be determined by thesettings of the modules, keeping the interconnections fixed. Suchswitching networks usually have regular interconnection patterns, andmodules which sit in one of two states, as illustrated in FIGS. 2a and2b, in which the two input lines are either exchanged or bypassed. Anumber of networks of this format exist each having a control structureto specify the setting of the modules to achieve a certain overallpermutation.

Other classes of computers are possible when the modules performadditional processing. If the modules are AND gates and OR gates then aprogrammable logic array can be built by using perfect shuffle orbutterfly interconnections. A fast Fourier transform machine has beenproposed where the interconnections are perfect shuffles and the modulesperform a weighted sum and difference calculation. These and otherprocesses can be achieved in an optical two dimensional network of theconfiguration of the present invention.

Referring now to FIG. 3, a two-dimensional optical interconnect networkaccording to the present invention is shown in generalised form. Itcomprises three stages S₄ to S₇ each comprising one, two dimensionalinterconnect stage 6 followed by a two dimensional array of modules 8each module having a two-dimensional array of four inputs 10 and fouroutputs 12. The interconnections 6 permute the incoming lines in twodimensions.

Referring now to FIG. 4 there is shown a known one-dimensionalinterconnect network (D. E. Knuth, "Sorting and Searching: AddisonWesley (1973)) which will be used by way of example to explain the stepsby which a given one-dimensional network can be reconfigured to a twodimensional network according to the present invention.

The linear network depicted in FIG. 4 is a sorting network havinginterconnections 14 which are perfect shuffles and processingsub-modules 16 of which only exemplary ones are referenced for clarity.Several different numbers enter input lines 15; arrowed modules (16)output the higher number at the port pointed to, and unmarked modules 16always bypass. The numbers emerging at outputs 17 are in numerical fromleft to right order.

A perfect shuffle interconnection comprises the splitting of the stackof lines into two halves and interleaving them, as shown in FIG. 5.

If the 2⁴ ports labelled by the four binary bits abcd are shuffled itcan be considered as the barrel rolling of the binary addresses of theports. That is, the input port labelled abcd is shuffled to the outputport addressed bcda. When a channel arrives at a module at port abcd itcan leave from either abc0 or abc1 where the port it leaves depends onwhat the type of module is and on the destination address of the otherchannel arriving at the same module.

Consider now the routing effect of two consecutive stages of the sortingnetwork: a line arriving at abcd is shuffled to bcda, exchanged orbypassed in a module (16 or 18) to bcdA where A can be 0 or 1, shuffledagain to cdAb and finally switched to cdAB, again where B can be 0 or 1.

abcd

bcda

bcdA

cdAb

cdAB

The line has a choice of four output addresses AB=00, 01, 10 and 11.Also there are four incoming lines which might emerge from these fourports-those arriving from ab=00, 01, 10 and 11.

Consider now that the lines in the linear array are arranged in spaceinto a square array according to the rule

    abcd"(column bd, row ac).

The function of the two stages of the 1D network can be performed by oneof the stages of the 2D network shown in FIG. 3. The new interconnectionis a 2D perfect shuffle which is a horizontal perfect shuffle followedby a vertical perfect shuffle. One of these permutations has the effect

    (bd, ac)→(db, ca)

which corresponds to two 1D shuffles in succession. The effect of themodules in the two consecutive stages of the linear network is to fixthe two bits a and b in the address. A module in the two dimensionalnetwork operates on the four ports differing in the final bits of therow and column addresses, a and b again, so one 4×4 module can be madeto do the same operations as all the relevant modules in the two stageson the old network. That is, by mapping the lines from a 1D to a 2Darray according to the rule above, the work of two stages of theoriginal network is done by one stage of the new network incorporating a2D perfect shuffle, and hence a two dimensional network can be built upusing this rule.

Considering now the operation of a 2D module in more detail. Each linksports (do, co), (do, cl), (dl, co) and (dl, cl). First bit a is fixed,then bit b, so the module can be regarded as being split into fourtwo-input, two-output sub-modules as in FIG. 6. These sub-modules arefour of the modules in FIG. 4 moved in space, and it is readilydeducible which four are associated in each module by using the mappingrule. The 2D module need not be physically separated into the four 2×2sub-modules as long as the module as whole is functionally identical tosuch a concentration of sub-modules as shown in FIG. 6.

The exchange/bypass decisions of the original network generate a sortedoutput of the network, but the output of the equivalent 2D network willhave the channel with the nth destination address at the port which isthe mapping of port n in the linear array. This scrambling of lines iswholly determined in advance and is functionally unimportant; if it isrequired to sort into a more visible order then the destinationaddresses can be modified at the start, or equivalently the modules canbe set according to the reverse-mapped addresses.

A single exemplary two dimensional network has been described above. Thestarting point was a one dimensional network. Consideration will now begiven to whether and how any two dimensional network according to thepresent invention can be constructed from a linear one, independent ofthe function of the modules and the interconnection pattern.

In analogy to the treatment of the perfect shuffle sorting networkabove, two consecutive stages can be concatenated into one stage of a 2Dnetwork by regarding the modules as being moved around in space. It maynot be possible for one interconnection followed by a layer of 4×4modules to do the work of two, one dimensional stages comprising aninterconnection, a 2×2 module as an interconnection and a final 2×2module sequence. Whatever the function of the modules in FIG. 2 we know(referring now to FIG. 7) that the intermediate module output X' is afunction of X and Y.

    X'=X'(X,Y)

and similarly for three of the other intermediate outputs

    Y'=Y'(X,Y)

    W'=W'(W,Z)

    Z'=Z'(W,Z)

The final module outputs X" and Z" which are functions of X' and Z'

    X"=X"(X',Z')

    Z"=Z"(X',Z')

so,

    X"=X"(X,Y,Z,W)

    Z"=Z"(X,Y,Z,W)

In order that the functions X" and Z" be calculated by one twodimensional, four-input four-output processing module, it is necessaryfor the other two outputs, Y" and W", to be functions of the same fourinputs

    Y"=Y"(X,Y,Z,W)

    W"=W"(X,Y,Z,W)

which can only be achieved if intermediate results Y' and W' meet at acommon module.

    Y"=Y"(Y',W')

    W"=W"(Y',W')

This imposes a restriction on the second of the two interconnects ofFIG. 6, which can be summarised as follows-

The complement of a line emerging from a module is defined to be theother line coming out of it. For any two lines which are the two inputsto a module, the complements of these two lines must also meet at acommon module.

If an interconnect does not satisfy this condition then it is notpossible to concatenate the consecutive stages of FIG. 7 into thefunctionally identical single stage of two dimensional 4×4 modulesaccording to the present invention.

In principle, for a network satisfying the interconnect condition asstated above, it is always possible to pick up the lines in the lineararrangement of FIG. 1 and move them into a two dimensional array as inFIG. 3. There will be many ways to do this mapping, but what is soughtis a 2D interconnection which can readily be achieved using a simpleoptical arrangement. An example is the special mapping applied to theperfect shuffle network. If a successful mapping scheme can be foundthen the task of generating a 2D network out of its linear counterpartis complete.

I claim:
 1. An optical interconnect network comprising:at least onestage which has an optical interconnect stage connecting atwo-dimensional array of interconnect input ports to a two-dimensionalarray of interconnect output ports; an array of optical processingmodules each module having a two-dimensional array of module inputports, optically coupled to a respective interconnect output port, and atwo dimensional array of module output ports characterised in that eachmodule defines a first and a second pair of two-input, two-output,processing sub-modules each of which performs a logic function on thedata supplied to its two inputs and generates processed data on its twooutputs and in which each input of each of the second pair of processingsub-modules is connected to a respective output of the first pair ofprocessing sub-modules, and wherein the inputs of each second processingsub-module are connected to the outputs from different first processingsub-modules.
 2. A network as in claim 1 in which each processingsub-module has two states, one state in which the inputs are exchanged,and a second state in which they are not exchanged.
 3. A network as inclaim 1 in which each processing sub-module performs weighted sum anddifference calculations, the network being configured to perform a fastFourier transform.
 4. A network as in claim 1 in which theinterconnection stage performs a perfect 2-D shuffle between theinterconnect input ports and interconnect output ports.
 5. A network asin claim 1 in which each sub-module defines an AND or an OR operationwhereby the network comprises a programmable logic array.
 6. Atwo-dimensional optical signal interconnect network comprising:atwo-dimensional array of two-dimensional optical signal processingmodules; each of said modules having four input ports and four outputports and including optical signal processing means including a firstpair of one-dimensional two-input, two-output optical signal processorscascaded with a second pair of one-dimensional two-input, two outputoptical signal processors, an output from each of the first processorsbeing connected to a respective input of each of the second processors.7. A network as in claim 6 wherein each one-dimensional processor iscapable of passing signals presented on two inputs a, b to its twooutputs a', b' either in the same order a', b' or in exchanged order b',a'.